The evolution of integrated circuits (IC) has led to designs of ever-increasing density and complexity. With these increased levels of integration, artisans within the IC industry often seek various goals for manufacturability, performance and functionality. For example, artisans may seek to design integrated circuits operable to incorporate a large number of different devices of various operabilities so as to assist more versatile integrations and applications. Further, they may also seek to reduce power dissipation by scaling down voltage levels, which may also accommodate reduction in device geometries. In some applications, however, the reduced geometries and reduced voltage levels for the typical CMOS circuit may compromise its speed of operation or immunity to noise.
Typically, different logic families are characterized with distinct properties suited for different goals. For example, current mode logic (CML) may typically be designated for high speed applications, but may come with an expense of high current levels and power dissipation. On the other hand, CMOS logic is generally directed towards low power applications. The power dissipation for customary CMOS logic is generally related to the dynamic needs required during signal transitions for charging or discharging the capacitance of gates within the CMOS circuits. The inherent capacitance of the gates, in turn, may be understood to limit the speed of operation of the CMOS circuits—presenting a trade-off to the low power benefits.
In a particular known system such as a CMOS synchronous circuit, a plurality of registers may be operable to store and/or sequence between various states. The operative speed for the system typically may depend on at least three timing parameters of the registers—setup time, hold time and propagation delay.
In the case of a master-slave register, a gatable switch generally is disposed between the master and slave portions of the master-slave register, which may be operable to enable selective transfer of data therebetween. Another gatable switch at the input may further enable selective application of data to the master portion of the register. These upstream and downstream gatable switches typically are driven by opposite phase renderings of a clock signal.